WP7: Digital signal processing

In this Work Package, the techniques of signal processing using software-defined radio (SDR) receiver systems will be developed to be suitable for parallel processing of signals from a phased array radar. The development will initially be done via laboratory set-ups of hardware and software, followed by a field trial of the developed units, which will establish their reliability and performance.

While the FP6 Design Study produced detailed designs for many parts of the new radar, the system was sufficiently far from construction, and technology advancing so rapidly in many areas, that although the required performance could already be delivered by existing hardware, more capable subsystems were certain to be available before system construction. It was thus appropriate to delay a final choice until the Preparatory Phase, in order to take full advantage of improvements in cost and performance.

The FP6 Design Study suggested a beam-forming and signal processing solution based throughout on the use of custom-built Field Programmable Gate Array (FPGA) hardware. This can, however be significantly simplified by combining FPGA based sampling and first stages of processing with the use of commercial SDR and off-the-shelf computing in the later stages of processing. Such system set-up would be directly compatible with the multi-purpose codes in WP11 as well as with many other parts of processing, be easier to implement in an operations environment. This approach potentially offers great promise in terms of their performance and flexibility but needs further evaluation before a decision can be made.

Because of the integral connection between hardware and software, this Work Package will be very closely coordinated with WP11 (software theory and implementation). It will also be closely coordinated with the science requirements package (WP3), receiving user requirements from the science community and advising the science users on the constraints imposed by the selected signal processing solution.

This Work Package contains the following activities:

  • Development of FPGA code for the sampler systems.
  • Acquisition of sampling hardware with which to perform the testing.
  • Integration of the sampling hardware with the analog front end hardware.
  • Field-testing and demonstration of the signal processing and beam-forming units.
  • Design of a clock synchronisation system to be used in the EISCAT_3D system.