Milestone 9.2: Revision of the exciter design finalised

A fully digital exciter design based on an off-the-shelf digital up-converter chip is developed as part of this Work Package. An initial prototype was produced and in operation (Milestone 9.1) in May 2011. The second prototype is a triple channel exciter, comprising three synchronised AD9957 QDUCs running off a common clock and being modulated by individually preprocessed baseband data streams from an FPGA controller. The revision of the design of the prototype exciter is Milestone 9.2.

This Milestone was reached in September 2011.